1. Field
This disclosure relates generally to split-gate flash cell arrays, and more specifically, to systems and methods to mitigate program gate disturb in split-gate flash cell arrays.
2. Related Art
Within a split gate memory cell array, each row of memory cells may be coupled to a control gate driver which drives a required voltage level onto the control gates of the split gate memory cells in accordance with the desired operation. For example, the voltage applied to the control gate of a memory cell depends on whether the desired operation of that memory cell is a program select operation, a program deselect operation, an erase operation, an erase verify operation, a program verify operation, etc. However, this may result in high voltages being applied to other control gates within the array even when the particular memory cell is not the subject of the instant operation. Therefore, a need exists for systems and methods to mitigate program gate disturb in split-gate flash cell arrays.